//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
//  Version and Release Control Information:
//
//  File Revision       : 129771
//
//  Date                :  2012-05-11 11:13:49 +0100 (Fri, 11 May 2012)
//
//  Release Information : PL401-r0p1-00eac0
//
//------------------------------------------------------------------------------
//  File Purpose        : This module is used with a single multi-layer
//                        map-layer to select the required add channel to 
//                        route through to the external master interface
//   
//  Key Configuration Details-
//      - Selecting one of 2 slave interfaces
//
// Notes on port naming conventions- 
//
//     All AXI point to point connections can be considered a 
//     MasterInterface - SlaveInterface connection. 
//
//     The AXI ports on the NIC400 A3BM are named as follows-  
//
//     *_m<n> suffix to denote a MasterIf (connect to external AXI slave)
//     *_s0 suffix to denote the SlaveIf (connect to external AXI master) 
//
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Module Declaration
//------------------------------------------------------------------------------

module nic400_switch2_add_sel_ml2_ysyx_rv32
  (
    // MasterInterface 
    // Write Address Channel
    awuser_m,
    awid_m,
    awaddr_m,
    awlen_m,
    awsize_m,
    awburst_m,
    awlock_m,
    awcache_m,
    awprot_m,
    awvalid_m,
    awvalid_vect_m,
    awready_m,
    aw_qv_m,
    // Read Address Channel
    aruser_m,
    arid_m,
    araddr_m,
    arlen_m,
    arsize_m,
    arburst_m,
    arlock_m,
    arcache_m,
    arprot_m,
    arvalid_m,
    arvalid_vect_m,
    arready_m,
    ar_qv_m,
    // Current selected write channel
    aw_sel,
    wvalid_m,
    wready_m,
    wlast_m,
    // Master Interface return channel handshake signals
    bvalid_m,
    bready_m,
    rvalid_m,
    rready_m,
    rlast_m,
    // SlaveInterface 0
    // Write Address Channel
    awuser_s0,
    awid_s0,
    awaddr_s0,
    awlen_s0,
    awsize_s0,
    awburst_s0,
    awlock_s0,
    awcache_s0,
    awprot_s0,
    awvalid_s0,
    awvalid_vect_s0,
    awready_s0,
    aw_qv_s0,
    // Read Address Channel
    aruser_s0,
    arid_s0,
    araddr_s0,
    arlen_s0,
    arsize_s0,
    arburst_s0,
    arlock_s0,
    arcache_s0,
    arprot_s0,
    arvalid_s0,
    arvalid_vect_s0,
    arready_s0,
    ar_qv_s0,

    // SlaveInterface 1
    // Write Address Channel
    awuser_s1,
    awid_s1,
    awaddr_s1,
    awlen_s1,
    awsize_s1,
    awburst_s1,
    awlock_s1,
    awcache_s1,
    awprot_s1,
    awvalid_s1,
    awvalid_vect_s1,
    awready_s1,
    aw_qv_s1,
    // Read Address Channel
    aruser_s1,
    arid_s1,
    araddr_s1,
    arlen_s1,
    arsize_s1,
    arburst_s1,
    arlock_s1,
    arcache_s1,
    arprot_s1,
    arvalid_s1,
    arvalid_vect_s1,
    arready_s1,
    ar_qv_s1,

    // bchannel mask 
    wr_cnt_empty,
    // Miscelaneous connections
    aclk,
    aresetn
  );

  // ---------------------------------------------------------------------------
  //  parameters
  // ---------------------------------------------------------------------------


  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------

  // MasterInterface 

  // Write Address Channel
  output [3:0]      awuser_m;
  output [3:0]      awid_m;
  output [31:0]     awaddr_m;
  output [7:0]      awlen_m;
  output [2:0]      awsize_m;
  output [1:0]      awburst_m;
  output            awlock_m;
  output [3:0]      awcache_m;
  output [2:0]      awprot_m;
  output            awvalid_m;
  output            awvalid_vect_m;
  input             awready_m;
  output [3:0]      aw_qv_m;
   
  // Read Address Channel
  output [3:0]      aruser_m;
  output [3:0]      arid_m;
  output [31:0]     araddr_m;
  output [7:0]      arlen_m;
  output [2:0]      arsize_m;
  output [1:0]      arburst_m;
  output            arlock_m;
  output [3:0]      arcache_m;
  output [2:0]      arprot_m;
  output            arvalid_m;
  output            arvalid_vect_m;
  input             arready_m;
  output [3:0]      ar_qv_m;
   
    // Current selected write channel
  output [1:0]      aw_sel;
  input             wvalid_m;
  input             wready_m;
  input             wlast_m;
  // Master Interface return channel handshake signals
  input             bvalid_m;
  input             bready_m;
  input             rvalid_m;
  input             rready_m;
  input             rlast_m;
  // SlaveInterface 0
  // Write Address Channel
  input  [3:0]      awuser_s0;
  input  [3:0]      awid_s0;
  input  [31:0]     awaddr_s0;
  input  [7:0]      awlen_s0;
  input  [2:0]      awsize_s0;
  input  [1:0]      awburst_s0;
  input             awlock_s0;
  input  [3:0]      awcache_s0;
  input  [2:0]      awprot_s0;
  input             awvalid_s0;
  input             awvalid_vect_s0;
  output            awready_s0;
  input  [3:0]      aw_qv_s0;
   
  // Read Address Channel
  input  [3:0]      aruser_s0;
  input  [3:0]      arid_s0;
  input  [31:0]     araddr_s0;
  input  [7:0]      arlen_s0;
  input  [2:0]      arsize_s0;
  input  [1:0]      arburst_s0;
  input             arlock_s0;
  input  [3:0]      arcache_s0;
  input  [2:0]      arprot_s0;
  input             arvalid_s0;
  input             arvalid_vect_s0;
  output            arready_s0;
  input  [3:0]      ar_qv_s0;


  // SlaveInterface 1
  // Write Address Channel
  input  [3:0]      awuser_s1;
  input  [3:0]      awid_s1;
  input  [31:0]     awaddr_s1;
  input  [7:0]      awlen_s1;
  input  [2:0]      awsize_s1;
  input  [1:0]      awburst_s1;
  input             awlock_s1;
  input  [3:0]      awcache_s1;
  input  [2:0]      awprot_s1;
  input             awvalid_s1;
  input             awvalid_vect_s1;
  output            awready_s1;
  input  [3:0]      aw_qv_s1;
   
  // Read Address Channel
  input  [3:0]      aruser_s1;
  input  [3:0]      arid_s1;
  input  [31:0]     araddr_s1;
  input  [7:0]      arlen_s1;
  input  [2:0]      arsize_s1;
  input  [1:0]      arburst_s1;
  input             arlock_s1;
  input  [3:0]      arcache_s1;
  input  [2:0]      arprot_s1;
  input             arvalid_s1;
  input             arvalid_vect_s1;
  output            arready_s1;
  input  [3:0]      ar_qv_s1;


  // bchannel mask 
  output            wr_cnt_empty;
  // Miscelaneous connections
  input             aclk;
  input             aresetn;

  //----------------------------------------------------------------------------
  // Wires 
  //----------------------------------------------------------------------------
  
  
  wire   [1:0]      aw_valid_vector;
  wire   [1:0]      ar_valid_vector;
  wire   [1:0]      aw_sel_i;
  wire   [1:0]      ar_sel_i;
  wire              last_rd;
  // Masked Write Address Channel Inputs
  wire   [3:0]      awuser_masked0;
  wire   [3:0]      awid_masked0;
  wire   [31:0]     awaddr_masked0;
  wire   [7:0]      awlen_masked0;
  wire   [2:0]      awsize_masked0;
  wire   [1:0]      awburst_masked0;
  wire              awlock_masked0;
  wire   [3:0]      awcache_masked0;
  wire   [2:0]      awprot_masked0;
  wire   [3:0]      aw_qv_masked0;
  wire              awvalid_masked0;
  wire              awvalid_vect_masked0;
  // Masked Read Address Channel Inputs
  wire   [3:0]      aruser_masked0;
  wire   [3:0]      arid_masked0;
  wire   [31:0]     araddr_masked0;
  wire   [7:0]      arlen_masked0;
  wire   [2:0]      arsize_masked0;
  wire   [1:0]      arburst_masked0;
  wire              arlock_masked0;
  wire   [3:0]      arcache_masked0;
  wire   [2:0]      arprot_masked0;
  wire   [3:0]      ar_qv_masked0;
  wire              arvalid_masked0;
  wire              arvalid_vect_masked0;

  // Masked Write Address Channel Inputs
  wire   [3:0]      awuser_masked1;
  wire   [3:0]      awid_masked1;
  wire   [31:0]     awaddr_masked1;
  wire   [7:0]      awlen_masked1;
  wire   [2:0]      awsize_masked1;
  wire   [1:0]      awburst_masked1;
  wire              awlock_masked1;
  wire   [3:0]      awcache_masked1;
  wire   [2:0]      awprot_masked1;
  wire   [3:0]      aw_qv_masked1;
  wire              awvalid_masked1;
  wire              awvalid_vect_masked1;
  // Masked Read Address Channel Inputs
  wire   [3:0]      aruser_masked1;
  wire   [3:0]      arid_masked1;
  wire   [31:0]     araddr_masked1;
  wire   [7:0]      arlen_masked1;
  wire   [2:0]      arsize_masked1;
  wire   [1:0]      arburst_masked1;
  wire              arlock_masked1;
  wire   [3:0]      arcache_masked1;
  wire   [2:0]      arprot_masked1;
  wire   [3:0]      ar_qv_masked1;
  wire              arvalid_masked1;
  wire              arvalid_vect_masked1;

  // Mask control signals to remove a slave interface from the arb scheme
  wire   [1:0]      mask_w;
  wire   [1:0]      mask_r;

  // Internal Master Interface Write Address Channel
  wire   [3:0]      awuser_m_i;
  wire   [3:0]      awid_m_i;
  wire   [31:0]     awaddr_m_i;
  wire   [7:0]      awlen_m_i;
  wire   [2:0]      awsize_m_i;
  wire   [1:0]      awburst_m_i;
  wire              awlock_m_i;
  wire   [3:0]      awcache_m_i;
  wire   [2:0]      awprot_m_i;
  wire              awvalid_m_i;
  wire              awvalid_vect_m_i;
  wire              awready_m_i;
  wire   [3:0]      aw_qv_m_i;
   
  // Internal Master Interface Read Address Channel
  wire   [3:0]      aruser_m_i;
  wire   [3:0]      arid_m_i;
  wire   [31:0]     araddr_m_i;
  wire   [7:0]      arlen_m_i;
  wire   [2:0]      arsize_m_i;
  wire   [1:0]      arburst_m_i;
  wire              arlock_m_i;
  wire   [3:0]      arcache_m_i;
  wire   [2:0]      arprot_m_i;
  wire              arvalid_m_i;
  wire              arvalid_vect_m_i;
  wire              arready_m_i;
  wire   [3:0]      ar_qv_m_i;



  // Instantiate internal slave interface wires
  // SlaveInterface 0
  // Write Address Channel
  wire   [3:0]      awuser_s0_i;
  wire   [3:0]      awid_s0_i;
  wire   [31:0]     awaddr_s0_i;
  wire   [7:0]      awlen_s0_i;
  wire   [2:0]      awsize_s0_i;
  wire   [1:0]      awburst_s0_i;
  wire              awlock_s0_i;
  wire   [3:0]      awcache_s0_i;
  wire   [2:0]      awprot_s0_i;
  wire              awvalid_s0_i;
  wire              awvalid_vect_s0_i;
  wire              awready_s0_i;
  wire   [3:0]      aw_qv_s0_i;
  
  // Read Address Channel
  wire   [3:0]      aruser_s0_i;
  wire   [3:0]      arid_s0_i;
  wire   [31:0]     araddr_s0_i;
  wire   [7:0]      arlen_s0_i;
  wire   [2:0]      arsize_s0_i;
  wire   [1:0]      arburst_s0_i;
  wire              arlock_s0_i;
  wire   [3:0]      arcache_s0_i;
  wire   [2:0]      arprot_s0_i;
  wire              arvalid_s0_i;
  wire              arvalid_vect_s0_i;
  wire              arready_s0_i;
  wire   [3:0]      ar_qv_s0_i;
  

  // SlaveInterface 1
  // Write Address Channel
  wire   [3:0]      awuser_s1_i;
  wire   [3:0]      awid_s1_i;
  wire   [31:0]     awaddr_s1_i;
  wire   [7:0]      awlen_s1_i;
  wire   [2:0]      awsize_s1_i;
  wire   [1:0]      awburst_s1_i;
  wire              awlock_s1_i;
  wire   [3:0]      awcache_s1_i;
  wire   [2:0]      awprot_s1_i;
  wire              awvalid_s1_i;
  wire              awvalid_vect_s1_i;
  wire              awready_s1_i;
  wire   [3:0]      aw_qv_s1_i;
  
  // Read Address Channel
  wire   [3:0]      aruser_s1_i;
  wire   [3:0]      arid_s1_i;
  wire   [31:0]     araddr_s1_i;
  wire   [7:0]      arlen_s1_i;
  wire   [2:0]      arsize_s1_i;
  wire   [1:0]      arburst_s1_i;
  wire              arlock_s1_i;
  wire   [3:0]      arcache_s1_i;
  wire   [2:0]      arprot_s1_i;
  wire              arvalid_s1_i;
  wire              arvalid_vect_s1_i;
  wire              arready_s1_i;
  wire   [3:0]      ar_qv_s1_i;
  



  //----------------------------------------------------------------------------
  // Registers 
  //----------------------------------------------------------------------------

  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------
  // SlaveInterface 0
  // Write Address Channel
  assign awuser_s0_i = awuser_s0;
  assign awid_s0_i = awid_s0;
  assign awaddr_s0_i = awaddr_s0;
  assign awlen_s0_i = awlen_s0;
  assign awsize_s0_i = awsize_s0;
  assign awburst_s0_i = awburst_s0;
  assign awlock_s0_i = awlock_s0;
  assign awcache_s0_i = awcache_s0;
  assign awprot_s0_i = awprot_s0;
  assign awvalid_s0_i = awvalid_s0;
  assign awvalid_vect_s0_i = awvalid_vect_s0;
  assign aw_qv_s0_i = aw_qv_s0;
  assign awready_s0 = awready_s0_i;
   
  // Read Address Channel
  assign aruser_s0_i = aruser_s0;
  assign arid_s0_i = arid_s0;
  assign araddr_s0_i = araddr_s0;
  assign arlen_s0_i = arlen_s0;
  assign arsize_s0_i = arsize_s0;
  assign arburst_s0_i = arburst_s0;
  assign arlock_s0_i = arlock_s0;
  assign arcache_s0_i = arcache_s0;
  assign arprot_s0_i = arprot_s0;
  assign arvalid_s0_i = arvalid_s0;
  assign arvalid_vect_s0_i = arvalid_vect_s0;
  assign ar_qv_s0_i = ar_qv_s0;
  assign arready_s0 = arready_s0_i;

  // SlaveInterface 1
  // Write Address Channel
  assign awuser_s1_i = awuser_s1;
  assign awid_s1_i = awid_s1;
  assign awaddr_s1_i = awaddr_s1;
  assign awlen_s1_i = awlen_s1;
  assign awsize_s1_i = awsize_s1;
  assign awburst_s1_i = awburst_s1;
  assign awlock_s1_i = awlock_s1;
  assign awcache_s1_i = awcache_s1;
  assign awprot_s1_i = awprot_s1;
  assign awvalid_s1_i = awvalid_s1;
  assign awvalid_vect_s1_i = awvalid_vect_s1;
  assign aw_qv_s1_i = aw_qv_s1;
  assign awready_s1 = awready_s1_i;
   
  // Read Address Channel
  assign aruser_s1_i = aruser_s1;
  assign arid_s1_i = arid_s1;
  assign araddr_s1_i = araddr_s1;
  assign arlen_s1_i = arlen_s1;
  assign arsize_s1_i = arsize_s1;
  assign arburst_s1_i = arburst_s1;
  assign arlock_s1_i = arlock_s1;
  assign arcache_s1_i = arcache_s1;
  assign arprot_s1_i = arprot_s1;
  assign arvalid_s1_i = arvalid_s1;
  assign arvalid_vect_s1_i = arvalid_vect_s1;
  assign ar_qv_s1_i = ar_qv_s1;
  assign arready_s1 = arready_s1_i;


  //----------------------- Address channel Mask control ----------------------

nic400_switch2_maskcntl_ml2_ysyx_rv32 u_nic400_switch2_maskcntl_ml2_ysyx_rv32 (
        // Master Interface address channel handshake signals
        .awvalid_m    (awvalid_m_i),
        .awready_m    (awready_m_i),
        .arvalid_m    (arvalid_m_i),
        .arready_m    (arready_m_i),
        .wvalid_m     (wvalid_m),
        .wready_m     (wready_m),
        .wlast_m      (wlast_m),

        // Master Interface return channel handshake signals
        .bvalid_m     (bvalid_m),
        .bready_m     (bready_m),
        .rvalid_m     (last_rd),
        .rready_m     (rready_m),
        // Arbitration mask vectors
        .wr_cnt_empty (wr_cnt_empty),
        .mask_w       (mask_w),
        .mask_r       (mask_r),
        // Miscelaneous connections
        .aclk         (aclk),
        .aresetn      (aresetn)
);


   assign last_rd = (rvalid_m & rlast_m);
   // Build a vector of write valids, one bit per attached slave interface
   assign aw_valid_vector[0] = awvalid_s0_i;
   assign aw_valid_vector[1] = awvalid_s1_i;
   // Build a vector of read valids, one bit per attached slave interface
   assign ar_valid_vector[0] = arvalid_s0_i;
   assign ar_valid_vector[1] = arvalid_s1_i;

  //----------------------- Address channel arbitration -----------------------
nic400_switch2_add_arb_ml2_ysyx_rv32 u_nic400_switch2_aw_arb_ml2_ysyx_rv32 (
        // Address Select Ouput 
        .a_sel          (aw_sel_i),
        // Input Select Criteria
        .a_valid_vector (aw_valid_vector),
        .aready         (awready_m_i),
        .mask           (mask_w),
        .qv0            (aw_qv_s0_i),
        .qv1            (aw_qv_s1_i),
        // Miscelaneous connections
        .aclk           (aclk),
        .aresetn        (aresetn)
);

nic400_switch2_add_arb_ml2_ysyx_rv32 u_nic400_switch2_ar_arb_ml2_ysyx_rv32 (
        // Address Select Ouput 
        .a_sel          (ar_sel_i),
        // Input Select Criteria
        .a_valid_vector (ar_valid_vector),
        .aready         (arready_m_i),
        .mask           (mask_r),
        .qv0            (ar_qv_s0_i),
        .qv1            (ar_qv_s1_i),
        // Miscelaneous connections
        .aclk          (aclk),
        .aresetn       (aresetn)
);

  //------------------------- Address channel Muxing --------------------------
  // Mask each slave interface address channel with its respective selction bit

    // Write Address Channel
    assign awuser_masked0  = awuser_s0_i & {4{aw_sel_i[0]}}; 
    assign awid_masked0    = awid_s0_i & {4{aw_sel_i[0]}};
    assign awaddr_masked0  = awaddr_s0_i & {32{aw_sel_i[0]}};
    assign awlen_masked0   = awlen_s0_i & {8{aw_sel_i[0]}};
    assign awsize_masked0  = awsize_s0_i & {3{aw_sel_i[0]}};
    assign awburst_masked0 = awburst_s0_i & {2{aw_sel_i[0]}};
    assign awlock_masked0  = awlock_s0_i & {1{aw_sel_i[0]}};
    assign awcache_masked0 = awcache_s0_i & {4{aw_sel_i[0]}};
    assign awprot_masked0  = awprot_s0_i & {3{aw_sel_i[0]}};
    assign aw_qv_masked0   = aw_qv_s0_i & {4{aw_sel_i[0]}};
    assign awvalid_masked0 = awvalid_s0_i & aw_sel_i[0];
    assign awvalid_vect_masked0 = awvalid_vect_s0_i & aw_sel_i[0];
  
    // Read Address Channel
    assign aruser_masked0  = aruser_s0_i & {4{ar_sel_i[0]}};
    assign arid_masked0   = arid_s0_i & {4{ar_sel_i[0]}};
    assign araddr_masked0  = araddr_s0_i & {32{ar_sel_i[0]}};
    assign arlen_masked0   = arlen_s0_i & {8{ar_sel_i[0]}};
    assign arsize_masked0  = arsize_s0_i & {3{ar_sel_i[0]}};
    assign arburst_masked0 = arburst_s0_i & {2{ar_sel_i[0]}};
    assign arlock_masked0  = arlock_s0_i & {1{ar_sel_i[0]}};
    assign arcache_masked0 = arcache_s0_i & {4{ar_sel_i[0]}};
    assign arprot_masked0  = arprot_s0_i & {3{ar_sel_i[0]}};
    assign ar_qv_masked0   = ar_qv_s0_i & {4{ar_sel_i[0]}};
    assign arvalid_masked0 = arvalid_s0_i & ar_sel_i[0];
    assign arvalid_vect_masked0 = arvalid_vect_s0_i & ar_sel_i[0];

    // Write Address Channel
    assign awuser_masked1  = awuser_s1_i & {4{aw_sel_i[1]}}; 
    assign awid_masked1    = awid_s1_i & {4{aw_sel_i[1]}};
    assign awaddr_masked1  = awaddr_s1_i & {32{aw_sel_i[1]}};
    assign awlen_masked1   = awlen_s1_i & {8{aw_sel_i[1]}};
    assign awsize_masked1  = awsize_s1_i & {3{aw_sel_i[1]}};
    assign awburst_masked1 = awburst_s1_i & {2{aw_sel_i[1]}};
    assign awlock_masked1  = awlock_s1_i & {1{aw_sel_i[1]}};
    assign awcache_masked1 = awcache_s1_i & {4{aw_sel_i[1]}};
    assign awprot_masked1  = awprot_s1_i & {3{aw_sel_i[1]}};
    assign aw_qv_masked1   = aw_qv_s1_i & {4{aw_sel_i[1]}};
    assign awvalid_masked1 = awvalid_s1_i & aw_sel_i[1];
    assign awvalid_vect_masked1 = awvalid_vect_s1_i & aw_sel_i[1];
  
    // Read Address Channel
    assign aruser_masked1  = aruser_s1_i & {4{ar_sel_i[1]}};
    assign arid_masked1   = arid_s1_i & {4{ar_sel_i[1]}};
    assign araddr_masked1  = araddr_s1_i & {32{ar_sel_i[1]}};
    assign arlen_masked1   = arlen_s1_i & {8{ar_sel_i[1]}};
    assign arsize_masked1  = arsize_s1_i & {3{ar_sel_i[1]}};
    assign arburst_masked1 = arburst_s1_i & {2{ar_sel_i[1]}};
    assign arlock_masked1  = arlock_s1_i & {1{ar_sel_i[1]}};
    assign arcache_masked1 = arcache_s1_i & {4{ar_sel_i[1]}};
    assign arprot_masked1  = arprot_s1_i & {3{ar_sel_i[1]}};
    assign ar_qv_masked1   = ar_qv_s1_i & {4{ar_sel_i[1]}};
    assign arvalid_masked1 = arvalid_s1_i & ar_sel_i[1];
    assign arvalid_vect_masked1 = arvalid_vect_s1_i & ar_sel_i[1];



    // Assign the Master Interface Address Channel Outputs from the 
    // Masked Slave Interface Inputs
    // Write Address Channel
    assign awuser_m_i  = awuser_masked0
                       | awuser_masked1;
    assign awid_m_i    = awid_masked0
                       | awid_masked1;
    assign awaddr_m_i  = awaddr_masked0
                       | awaddr_masked1;
    assign awlen_m_i   = awlen_masked0
                       | awlen_masked1;
    assign awsize_m_i  = awsize_masked0
                       | awsize_masked1;
    assign awburst_m_i = awburst_masked0
                       | awburst_masked1;
    assign awlock_m_i  = awlock_masked0
                       | awlock_masked1;
    assign awcache_m_i = awcache_masked0
                       | awcache_masked1;
    assign awprot_m_i  = awprot_masked0
                       | awprot_masked1;
    assign aw_qv_m_i   = aw_qv_masked0
                       | aw_qv_masked1;
    assign awvalid_m_i = (awvalid_masked0
                      | awvalid_masked1);
     assign awvalid_vect_m_i = (awvalid_vect_masked0
                      | awvalid_vect_masked1);
  
    // Read Address Channel
    assign aruser_m_i  = aruser_masked0
                       | aruser_masked1;
    assign arid_m_i    = arid_masked0
                       | arid_masked1;
    assign araddr_m_i  = araddr_masked0
                       | araddr_masked1;
    assign arlen_m_i   = arlen_masked0
                       | arlen_masked1;
    assign arsize_m_i  = arsize_masked0
                       | arsize_masked1;
    assign arburst_m_i = arburst_masked0
                       | arburst_masked1;
    assign arlock_m_i  = arlock_masked0
                       | arlock_masked1;
    assign arcache_m_i = arcache_masked0
                       | arcache_masked1;
    assign arprot_m_i  = arprot_masked0
                       | arprot_masked1;
    assign ar_qv_m_i   = ar_qv_masked0
                       | ar_qv_masked1;
    assign arvalid_m_i = (arvalid_masked0
                       | arvalid_masked1);
    assign arvalid_vect_m_i = (arvalid_vect_masked0
                       | arvalid_vect_masked1);

    // Mask the ready signals back to the current slave interface

    assign awready_s0_i     = awready_m_i & aw_sel_i[0];
    assign arready_s0_i     = arready_m_i & ar_sel_i[0];

    assign awready_s1_i     = awready_m_i & aw_sel_i[1];
    assign arready_s1_i     = arready_m_i & ar_sel_i[1];

    // Write Address Channel
    assign awuser_m       = awuser_m_i;
    assign awid_m         = awid_m_i;
    assign awaddr_m       = awaddr_m_i;
    assign awlen_m        = awlen_m_i;
    assign awsize_m       = awsize_m_i;
    assign awburst_m      = awburst_m_i;
    assign awlock_m       = awlock_m_i;
    assign awcache_m      = awcache_m_i;
    assign awprot_m       = awprot_m_i;
    assign aw_qv_m        = aw_qv_m_i;
    assign awvalid_m      = awvalid_m_i;
    assign awvalid_vect_m = awvalid_vect_m_i;
   
    // Read Address Channel
    assign aruser_m       = aruser_m_i;
    assign arid_m         = arid_m_i;
    assign araddr_m       = araddr_m_i;
    assign arlen_m        = arlen_m_i;
    assign arsize_m       = arsize_m_i;
    assign arburst_m      = arburst_m_i;
    assign arlock_m       = arlock_m_i;
    assign arcache_m      = arcache_m_i;
    assign arprot_m       = arprot_m_i;
    assign ar_qv_m        = ar_qv_m_i;
    assign arvalid_m      = arvalid_m_i;
    assign arvalid_vect_m = arvalid_vect_m_i;

    // Assign return ready signals
    assign awready_m_i    = awready_m;
    assign arready_m_i    = arready_m;

    // Output select signals
    assign aw_sel         = aw_sel_i;



endmodule



//  --=============================== End ====================================--

